Semiconductor memory device with shared data input/output line

Details Semiconductor memory device with shared data input/output line Semiconductor memory device with shared data input/output line

1997-10-08

1999-03-23

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365203, 36518908, 36518905, G11C 800

Patent

active

058869476

ABSTRACT:
The semiconductor memory device includes a clock signal generating circuit, a precharge circuit, a write circuit, and an input/output circuit. The clock signal generating circuit generates a second clock signal having a second state of a constant interval irrespective of a period of a first clock signal. The precharge circuit precharges a data input/output line in response to a precharge signal. The write circuit transfers, during a write operation, input data signal to the data input/output line each time the second clock signal is a first state under the state that a power signal and the precharge signal are the first state. The input/output circuit transfers data transmitted to the data input/output line to a cell.

REFERENCES:
patent: 5606526 (1997-02-01), Pilo
patent: 5751644 (1998-05-01), Ansel et al.

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