Cell structure for erasable programmable read-only memories

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

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Details

Other Related Categories

257316, 257401, H01L 2968

Type

Patent

Status

active

Patent number

051928728

Description

ABSTRACT:
A design for EPROMs, EEPROMs, and Flash EEPROMs is described which greatly increases the coupling coefficient of the cell and enhances cell access speed. The increase in control gate to floating gate coupling is due to a decrease in the capacitance between the floating gate and the substrate, which includes the drain, source, and channel. This increase in the coupling coefficient will allow for a smaller cell size and better program and erase characteristics. A reduction in the capacitance between the floating gate and the transistor drain will reduce the so-called drain coupling effect. Severe drain coupling could increase undesirable drain-to-source leakage. Finally, a structure comprising the invention has a faster cell access time resulting from the fact that half the cell channel region is directly controlled by the control gate. This half of the channel region will see higher effective vertical electric field from the control gate than the channel region covered by the floating gate. A high transistor current will be generated, thereby increasing the speed of the cell.

REFERENCES:
patent: 4853895 (1989-08-01), Mitchell et al.
patent: 5034798 (1991-07-01), Ohsima

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