Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-11-18

1997-11-25

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257306, 257309, 257390, 257401, 257774, H01L 2968

Patent

active

056915519

ABSTRACT:
In a semiconductor memory device, pitch of bit lines is made larger than pitch of word lines, and a storage node contact is positioned in each rectangular area surrounded by the bit lines and the word lines. The distance between centers of adjacent storage node contacts and the distance between centers of a bit line contact and an adjacent storage node contact are both made larger than the pitch of word lines. By this structure, planar area per unit memory cell can be increased, registration margin between the storage node and the storage node contact can be enlarged, short-circuit between the bit line and the storage node contact is prevented, and thus a memory cell structure of high production yield and high reliability can be realized.

REFERENCES:
patent: 5012309 (1991-04-01), Nakayama
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5324975 (1994-06-01), Kumagai et al.
Kawamoto et al., "A 1.28 .mu.m .sup.2 -Bit-Line Shielded Memory Cell Technology for 65Mb DRAMs", 1990 Symposium on VLSI Technology, pp. 13-14.
Ahn et al., "Bidirectional Matched Global Bit Line Scheme for High Density DRAMs", VLSI Circuit 1993, pp. 91-92.
Aoki et al., "A 1.5-V DRAM for Battery-Based Applications", IEEE Journal of Solid-State Circuits, vol., 24, No. 5 (Oct. 1989), pp. 1206-1211.

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