Semiconductor memory including stacked capacitor having a flat s

Details Semiconductor memory including stacked capacitor having a flat s Semiconductor memory including stacked capacitor having a flat s

1995-10-03

1998-02-10

Tran, Minh-Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257308, 257310, 257626, H01L 27108

Patent

active

057172366

ABSTRACT:
To enhance an electric characteristic of a capacitor by decreasing a leak current, and by eliminating a recess formed in the middle of a lower electrode. In order to cover a transistor, a first interlayer insulating film (10), and a second interlayer insulating film (11) as a stopper member of a CMP method thereon are sequentially formed, a contact hole (12) is formed, and the contact hole (12) is filled in by forming a polysilicon film. Polishing the polysilicon film by the CMP method, the second interlayer insulating film (11) is formed in a thickness of 30 to 100 nm. As a result, a polysilicon plug (14) with a flat upper surface free from recess is formed, and lower electrodes (15, 16) formed thereon are also films of uniform thickness without recess, so that recess is not formed either in the middle of a ferrodielectric film (21). Therefore, the sinking amount of an oxide film spacer (19) for framing a side surface of the lower electrodes (15, 16) is small, and forming of a metal wiring layer (24) is easier.

REFERENCES:
patent: 5335138 (1994-08-01), Sandhu et al.
patent: 5418388 (1995-05-01), Okudaira et al.
patent: 5561311 (1996-10-01), Hamamoto et al.
IEEE, pp. 34.4.1-34.4.4, 1994, Shigeo Onishi, et al., "A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure".

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