Multimedia computer architecture with multi-channel concurrent m

Details Multimedia computer architecture with multi-channel concurrent m Multimedia computer architecture with multi-channel concurrent m

1997-09-30

2000-06-13

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711146, 710128, G06F 1316

Patent

active

060761393

ABSTRACT:
A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.

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Video Electronics Standards Association, VESA.RTM., VM Channel.TM. Standard, Version 1.0, .COPYRGT. Copyright 1995, Revision Date: Dec. 1, 1993, pp. 1-81.

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