Hierarchical bus simple COMA architecture for shared memory mult

Details Hierarchical bus simple COMA architecture for shared memory mult Hierarchical bus simple COMA architecture for shared memory mult

1998-02-13

2000-11-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711145, 709213, G06F 1200

Patent

active

061483753

ABSTRACT:
A method of maintaining cache coherency in a shared memory multiprocessor system having a plurality of nodes, where each node itself is a shared memory multiprocessor. With this invention, an additional shared owner state is maintained so that if a cache at the highest level of cache memory in the system issues a read or write request to a cache line that misses the highest cache level of the system, then the owner of the cache line places the cache line on the bus interconnecting the highest level of cache memories.

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patent: 5835950 (1998-11-01), Cho et al.
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