Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-01-21
2000-11-14
Yoo, Do Hyun
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711151, G06F 1208
Patent
active
061483729
ABSTRACT:
A multi-level cache and method for operation thereof is presented for processing multiple cache system accesses simultaneously. The cache includes a first non-blocking cache receiving data access requests from a device in a processor, and a first miss queue storing entries corresponding to data access requests not serviced by the first non-blocking cache. A second non-blocking cache is provided and receives data access requests from the first miss queue, and a second miss queue stores entries corresponding to data access requests not serviced by the second non-blocking cache. A first arbiter arbitrates between two or more access requests to the first non-blocking cache. A second arbiter can be provided to arbitrate between two or more access requests to the second non-blocking cache.
The arbiter is capable of determining if an anticipatory stall signal should be asserted if any of the cache resources, such as a queuing structure, is becoming overloaded. Under such conditions, the arbiter anticipatorily asserts the stall signal to cut-off new cache access requests from the front-end of the processor. The arbiter then dynamically reprioritizes the pending access requests to the cache so that the overflow condition can be eliminated and normal operation can resume. The arbiter anticipatorily de-asserts the stall signal to the processor so that normal operations can resume.
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Mehrotra Sharad
Wong Michelle L.
McKay Philip
Portka Gary J.
Sun Microsystems Inc.
Yoo Do Hyun
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