Semiconductor memory device accessible at high speed

Details Semiconductor memory device accessible at high speed Semiconductor memory device accessible at high speed

1999-04-08

2000-06-13

Elms, Richard T.

Static information storage and retrieval

Read/write circuit

36518905, 36523003, 36523005, G11C 1604

Patent

active

060757280

ABSTRACT:
A DRAM includes a data transfer pipeline register group between a dynamic memory cell array and a static memory cell array, a first unidirectional read bus and a first unidirectional write bus connected between a data transfer bus group and the data transfer pipeline register group, and a second unidirectional write bus and a second unidirectional read bus connected between the data transfer pipeline register group and the static memory cell array. The operating frequency of the second unidirectional write bus and the second unidirectional read bus is N times the operating frequency of the first unidirectional read bus and the first unidirectional write bus. The number of lines of the second unidirectional write bus and the second unidirectional read bus is 1/N time the number of lines of the first unidirectional read bus and the first unidirectional write bus. The dynamic memory cell array is further divided into a hierarchical manner of main banks and subbanks.

REFERENCES:
patent: 5953257 (1999-09-01), Inoue et al.

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