Processor and method for out-of-order execution of instructions

Details Processor and method for out-of-order execution of instructions Processor and method for out-of-order execution of instructions

1996-03-15

1999-02-16

Eng, David Y.

G06F 928

Patent

active

058729488

ABSTRACT:
A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

REFERENCES:
patent: 5434987 (1995-07-01), Abramson et al.
patent: 5555432 (1996-09-01), Hinton et al.
patent: 5574935 (1996-11-01), Vidwans et al.
patent: 5606670 (1997-02-01), Abramson et al.
patent: 5699537 (1997-12-01), Sharangpani et al.

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