Staggered pipeline access scheme for synchronous random access m

Details Staggered pipeline access scheme for synchronous random access m Staggered pipeline access scheme for synchronous random access m

1998-04-21

1999-02-16

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365195, 365196, 365202, 36523006, 36523008, G11C 800

Patent

active

058727426

ABSTRACT:
A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an external address in the set-up time prior to the rising edge of the external clock. A timing and control circuit (18) generates a word line enable (WLE) signal in synchronism with the rising edge of the external clock. When active, WLE activates a word line driver (34), when inactive, WLE equalizes the bit lines. WLE is applied to a first delay circuit (60) to generate a sense signal (SA). SA activates a sense circuit (46) and deactivates the WLE signal. Consecutive pipelined accesses are achieved such that, as an address is decoded, the bit lines are equalizing and the data from the previous address are propagating through a data I/O path (16).

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