Processor bridge with dissimilar data registers which is operabl

Details Processor bridge with dissimilar data registers which is operabl Processor bridge with dissimilar data registers which is operabl

1998-06-15

2000-10-31

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

714 11, G06F 1300

Patent

active

061417181

ABSTRACT:
A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is operable to compare address and data phases of I/O accesses by the first and second processing sets. A direct memory access mechanism is operable to initiate a direct memory access operation to read from a corresponding location in each processor set into a respective dissimilar data register associated with each processing set. The bridge control mechanism is operable during the direct memory access operation to disregard differences in the data phase for the dissimilar data write access. As a result it is possible to transfer dissimilar data from the processors into the bridge in a combined (lockstep comparison) mode. In a subsequent phase the bridge control mechanism responds to a read destination address supplied in common by the first and second processing sets for a dissimilar data read access to supply data read from a determined one of the dissimilar data registers to the first and second processing sets. In this manner the data from one processing set can be copied to the other processing set while in a combined mode.

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