Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

1997-11-25

1999-10-19

Nelms, David

Static information storage and retrieval

Systems using particular element

Ferroelectric

365149, G11C 1122

Patent

active

059699795

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a ferroelectric memory device.


BACKGROUND ART

Recently, by using a ferroelectric material in the capacitor of memory cell, a ferroelectric memory device realizing nonvolatility of stored data is devised. The ferroelectric capacitor has a hysteresis characteristic, and if the electric field is zero, a residual polarization of different polarity depending on the hysteresis is left over. By expressing the stored data by the residual polarization of the ferroelectric capacitor, a nonvolatile memory device is realized. The specification of U.S. Pat. No. 4,873,664 discloses two types of ferroelectric memory device.
In a first type, a memory cell is composed of one transistor and one capacitor per bit (1T1C), and a ferroelectric capacitor for reference memory cell is provided in, for example, every 256 ferroelectric capacitors for main body memory cells (normal cells).
In a second type, without using ferroelectric capacitor for reference memory cell, a memory cell is composed of two transistors and two capacitors per bit (2T2C), in which a pair of complementary data are stored in a pair of ferroelectric capacitors for main body memory cell.
For a larger memory capacity, the 1T1C type is advantageous, and at this time, for low voltage operation and operation for a longer life, the design of ferroelectric capacitor for reference cell is important in the ferroelectric cell capacitor for main body memory cell.
As the ferroelectric material for composing capacitor, KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, and PbTiO.sub.3 --PbZrO.sub.3 are known among others. According to PCT International Disclosure No. WO93/12542 Publication, ferroelectric materials extremely small in fatigue as compared with PbTiO.sub.3 --PbZrO.sub.3 suited to ferroelectric memory device are also known.
The constitution of conventional ferroelectric memory device of 1T1C type is described briefly below.
FIG. 7 is a memory cell block diagram, FIG. 8 is a sense amplifier circuit diagram, and FIG. 9 is an operation timing chart.
In FIG. 7, C00 to C37 refer to ferroelectric capacitors for main body memory cells, CD00 to CD31 are ferroelectric capacitors for reference memory cells, CPD is a cell plate driver, and REW0 and REW1 are reference memory cell rewrite signal lines. In addition, SA0 to SA3 are sense amplifiers, and CP is a cell plate signal. And WL0 to WL7 are word lines, RWL0 and RWL1 are reference word lines, and BL0 to BL3, /BL0 to /BL3 are bit lines. In FIG. 8 and FIG. 9, BP is a bit line precharge signal, and /SAP, SAN are sense amplifier control signals. Besides, VSS is a grounding voltage, and VDD is a supply voltage.
In the memory cell composition, for example as shown in the diagrams, bit lines BL0 and /BL0 are connected to the sense amplifier SA0. Further, a ferroelectric capacitor for main body memory cell C00 is connected to the bit line BL0 through an N-channel MOS transistor Tr1 having word line WL0 as its gate. To the bit line /BL0, moreover, a ferroelectric capacitor for reference memory cell CD00 is connected through an N-channel MOS transistor Tr2 having reference word line RWL0 as its gate. The ferroelectric capacitors C00, CD00 are connected to the cell plate signal line CP which is driven by the cell plate driver CPD.
The bit lines /BL0 and /BL1 are connected through an N-channel MOS transistor Tr3 having the reference word line RWL0 as its gate. The bit line BL0 and ferroelectric capacitor for reference memory cell CD00 are connected through an N-channel MOS transistor Tr5 having the reference memory cell rewrite signal line REW0 as its gate.
As shown in FIG. 8, the sense amplifier SA0 is controlled by sense amplifier control signals /SAP, SAN, and the circuit is thus composed so that precharge of bit lines BL0 and /BL0 is controlled by the bit line precharge signal BP.
In this conventional ferroelectric memory device in 1T1C composition is based on a method of using two ferroelectric capacitors of nearly same size as the ferroelectric capacitor for main body

REFERENCES:
patent: 4873664 (1989-10-01), Eaton, Jr.
patent: 5297077 (1994-03-01), Imai et al.
patent: 5373463 (1994-12-01), Jones, Jr.
patent: 5572459 (1996-11-01), Wilson et al.
European Search Report for Int'l Appln. No. 97907378 dated Apr. 9, 1998.
Japanese language search report for Int'l Appln. No. PCT/JP97/00893.
English translation of Japanese search report for Int'l Appln. No. PCT/JP97/00893.

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