FPGA with hierarchical interconnect structure and hyperlinks

Details FPGA with hierarchical interconnect structure and hyperlinks FPGA with hierarchical interconnect structure and hyperlinks

1996-06-04

1998-04-21

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 38, H03K 19177, H03K 19173

Patent

active

057421811

ABSTRACT:
A programmable logic device including a plurality of programmable atomic logic elements (PALEs) where each PALE has a plurality of data inputs and generates a data output signal. The PALEs are logically arranged as a plurality of hierarchically coupled partitions. Each partition is defined by a unique set of the next lower hierarchy partitions and an interconnect bus that extends only to the unique set of the next lower partitions that are within that partition. The lowest level of hierarchy is one of the plurality of PALEs. A plurality of hyperlinks provided within each PALE programmably couples the PALE data output signal to each of the interconnect busses in each of the higher levels of hierarchy that include the PALE. Preferably, the PALE also includes a tunnel connection for coupling the PALE data output signal to adjacent neighbor PALEs without using the interconnect bus of any of the partitions.

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