Method and apparatus for memory prefetch operation of volatile n

Details Method and apparatus for memory prefetch operation of volatile n Method and apparatus for memory prefetch operation of volatile n

1997-09-05

2000-10-03

Nguyen, Hiep T

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711137, 711143, 712207, G06F 1208

Patent

active

061287032

ABSTRACT:
An apparatus and method for prefetching data into a cache memory system is provided. A prefetch instruction includes a hint type that allows a programmer to designate whether, during a data retrieval operation, a hit in the cache is to be ignored or accepted. If accepted, the prefetch operation completes. If ignored, the prefetch operation retrieves data from the main memory, even though the cache believes it contains valid data at the requested memory location. Use of this invention in a multiple bus master processing environment provides the advantages of using a cache memory, i.e., burst reads and a relatively large storage space as compared to a register file, without incurring disadvantages associated with maintaining data coherency between the cache and main memory systems.

REFERENCES:
patent: 5247639 (1993-09-01), Yamahata
patent: 5454093 (1995-09-01), Abdulhafiz et al.
patent: 5748938 (1998-05-01), Kahle

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