Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Patent
1998-06-05
2000-10-31
Smith, Matthew
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
438199, 438527, H01L 2100, H01L 2184
Patent
active
061401617
ABSTRACT:
Disclosed is a method for making a semiconductor integrated circuit device used to form a p-channel MOS field-effect transistor and a n-channel MOS field-effect transistor on a common SOI substrate with a structure that a first silicon layer, insulating film and a second silicon layer are layered;
wherein the steps from sectioning a SOI layer as the second silicon layer by insulation separation into a plurality of active regions to forming at least one gate electrode to be laid through gate insulating film on the surface of each of the plurality of active regions are conducted with no relation to the conductivity type of MOS field-effect transistor.
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Raynaud et al., "Sub-0.25 .mu.m Ultra-Thin SOI CMOS With A Single N+ Gate process For Low-Voltage And Low-Power Applications", Proceedings 1996 IEEE International SOI Conference, pp. 80, (1996).
Lee Calvin
NEC Corporation
Smith Matthew
LandOfFree
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