Semiconductor memory device with clocked column redundancy and t

Details Semiconductor memory device with clocked column redundancy and t Semiconductor memory device with clocked column redundancy and t

1997-06-03

1999-10-19

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

365201, G06F 1100

Patent

active

059681837

ABSTRACT:
A semiconductor memory device includes: a plurality of output data terminals; a matrix of memory cells including a plurality of groups of columns of memory cells, each group of columns being associated with a respective output data terminal; column selection means associated with the matrix of memory cells for selectively coupling one column for each of the group of columns to a respective sensing means driving the output data terminal; redundancy columns of redundancy memory cells for functionally replacing defective columns in the matrix; redundancy column selection means associated with the redundancy columns for selectively coupling one redundancy column to a redundancy sensing means; defective address storage means for storing defective addresses of the defective columns and identifying codes suitable for identifying the groups of columns wherein the defective columns are located, for comparing the defective addresses with a current address supplied to the memory device and for driving the redundancy column selection means for selecting a redundancy column when a current address supplied to the memory device coincides with one of the defective addresses. A shared bus including a plurality of signal lines is provided in the memory device for interconnecting a plurality of circuit blocks of the memory device and for transferring signals between the circuit blocks, the shared bus being selectively assignable to the circuit blocks in prescribed respective time intervals. The memory device also includes first bus assignment means associated with the defective address storage means and second bus assignment means associated with the sensing means.

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Horiguchi, M, Redundancy techniques for high density DRAMs, IEEE International test conference, pp. 22-29, May 1997.
European Search Report from European Patent Application 96830324.8, filed Jun. 6, 1996.

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