Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1997-06-13
2000-07-18
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711154, 711158, 710240, G06F 1200, G06F 1300
Patent
active
060921587
ABSTRACT:
A method and apparatus for arbitrating between command streams. The method unblocks high priority commands which are blocked and then selects any remaining high priority commands. Normal priority commands are selected after the high priority commands. A memory controller described includes a command queue block having a plurality of command queues, each being coupled to receive a different type of command. The memory controller also includes arbitration logic which, among other things, selects high priority read commands before high priority write commands. Memory interface logic generates memory accesses performing commands selected by the arbitration logic.
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Ajanovic Jasmin
Harriman David J.
Langendorf Brian K.
Bataille Pierre-Michel
Cabeca John W.
Draeger Jeffrey S.
Intel Corporation
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