Dynamic allocation and reallocation of buffers in links of chain

Details Dynamic allocation and reallocation of buffers in links of chain Dynamic allocation and reallocation of buffers in links of chain

1998-05-15

2000-07-18

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 22, 710 26, 710 57, G06F 1310, G06F 1202

Patent

active

060921277

ABSTRACT:
A system which performs chained direct memory access (DMA) operations, includes a working set of buffers, a first-in-first-out memory, a first DMA co-processor, a second DMA co-processor and a controlling processor. The working set of buffers are available for receiving data from chained DMA operations. The first-in-first-out memory store addresses of buffers, from the working set of buffers, which are available for immediate allocation. The first DMA co-processor and the second DMA co-processor perform the chained DMA operations. The controlling processor sets up the chained DMA operations and adds addresses of free buffers to the first-in-first-out memory. When performing a first chained DMA operation, the first DMA co-processor accesses the first-in-first-out memory to allocate for itself a first buffer from the queue of buffers when a first link in the first chained DMA operation requires a buffer. When the first buffer is filled, the first DMA co-processor immediately notifies the controlling processor. When performing a second chained DMA operation, the second DMA co-processor accesses the first-in-first-out memory to allocate for itself a second buffer from the queue of buffers when a first link in the second chained DMA operation requires a buffer. When the second buffer is filled, the second DMA co-processor immediately notifies the controlling processor.

REFERENCES:
patent: 5155830 (1992-10-01), Kurashige
patent: 5426639 (1995-06-01), Follett et al.
patent: 5430846 (1995-07-01), Moore
patent: 5687392 (1997-11-01), Radko
patent: 5765023 (1998-06-01), Leger et al.
patent: 5928339 (1999-07-01), Nishikawa
SYM53C875 PCI-SCSII/O Processor with Fast-20 Data Manual, available from Symbios Logic Inc., 4420 Arrowswest Drive, Colorado Springs, CO 80907-3439, pp., i, 5-4,6-5 through 6-7,6-20 through 6-24.

Affiliated with

Also associated with

Rating

Dynamic allocation and reallocation of buffers in links of chain does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic allocation and reallocation of buffers in links of chain, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic allocation and reallocation of buffers in links of chain will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2048532