Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1994-09-27
1996-05-21
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, 3652257, G11C 700
Patent
active
055196578
ABSTRACT:
A memory device includes a plurality of memory arrays each having a plurality of memory cells arranged in rows and columns, and at least one spare arrays having the same arrangement of memory cells as the memory array. A word line connecting a row of memory cells at a first address in a memory array is replaced by a spare word line connecting a row of memory cells at the first address in the spare memory array. Such a replacement scheme provides a word line by word line replacement and an array by array replacement with a simplified replacement control circuit and reduced area penalty.
REFERENCES:
patent: 4376300 (1983-03-01), Tsang
patent: 5083294 (1992-01-01), Okajima
patent: 5293348 (1994-03-01), Abe
patent: 5307316 (1994-04-01), Takemae
"DRAM Technologies for File Applications", Goro Kitsukawa et al., 1993 IEEE ISSCC, Digest of Technical Papers, Feb. 24, 1993, pp. 48-49.
Mitsubishi Denki & Kabushiki Kaisha
Popek Joseph A.
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