Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-09-19
2000-07-18
Loke, Steven H.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257408, 257409, H01L 2976, H01L 2994, H01L 31062
Patent
active
060911115
ABSTRACT:
A high voltage MOS device includes a P-type substrate having an N-type buried layer formed therein. An N-type epitaxial layer overlies the substrate and a P-type well is formed in the epitaxial layer. A source region is formed in the well such that the source region is directly in contact with the well. No intermediate layer is disposed between the source region and the well. A drain region includes an extended drain region. The extended drain region, which is formed within and in contact with the well, comprises different dopant species and has a maximum dopant concentration of 3.5.times.10.sup.17 cm.sup.-3. A heavily doped main drain region is formed within and in contact with the extended drain region. The source region and extended drain region define a channel region therebetween in the well. An insulator is on a surface of the well over the channel region. A gate is over the insulator.
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Hsia et al., "Polysilicon Oxidation Self-Aligned MOS (POSA MOS)--A New Self-Aligned Double Source/Drain Ion Implantation Technique for VLSI", IEEE Electron Device Letters, vol. EDL-3, No. 2, Feb. 1982, New York, USA, pp. 40-42.
Yoshikawa et al., "A Reliable Profiled Lightly Doped Drain (PLD) Cell For High-Density Submicrometer EPROM's and Flash EEPROM's", IEEE Transactions on Electron Devices, vol. 37, No. 2, Apr. 1990, New York, USA, pp. 999-1006.
Demirlioglu Esin Kutlu
El-Diwany Monir H.
Kwok Edward C.
Loke Steven H.
National Semiconductor Corporation
Woo Philip W.
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