Surface charge signal processing apparatus

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364862, 357 24, G06G 719, G11C 1140

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active

044465327

ABSTRACT:
A plurality of charge storage cells, each including first and second storage regions and corresponding first and second electrodes insulatingly overlying the storage regions are provided in a semiconductor substrate. Means are provided for introducing into each of the first charge storage regions a respective quantity of charge proportional to a respective sample of an analog signal. Means are provided for developing a plurality of voltage waveforms, each of the waveforms including a series of periods, and each period constituted of first and second subperiods. Means are provided for applying each of the voltage waveforms to a respective one of the second electrodes of the cells. A high absolute level of a waveform applied to a second electrode of a cell causing charge in the first storage region thereof to transfer to the second storage region thereof and a low absolute level of the waveform applied to a second electrode of a cell causing charge in the second storage region thereof to transfer to the first storage region thereof. Each of the waveforms has a low absolute level during a first subperiod and an absolute level which is either high or low during a second subperiod in response to a respective reference signal, whereby charge in each cell is transferred between the first and second charge storage regions thereof in a time sequence determined by a respective reference signal. Means are provided connected in circuit with the first storage electrodes for sensing the total net charge transferred to and from the first charge storage regions during a common period of the voltage waveforms.

REFERENCES:
patent: 4058716 (1977-11-01), Goldberg
patent: 4058717 (1977-11-01), Engeler
patent: 4084257 (1978-04-01), Burke et al.
patent: 4403299 (1983-09-01), Engeler
R. F. Harland, AB 8182-Bit Shift Register, Proceedings of ISSCC, Feb. 14, 1973, pp. 54-55.

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