Non-volatile semiconductor memory and the testing method for the

Details Non-volatile semiconductor memory and the testing method for the Non-volatile semiconductor memory and the testing method for the

1981-01-27

1983-07-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

365207, 365185, G11C 1140

Patent

active

043934757

ABSTRACT:
A nonvolatile semiconductor memory device formed of a plurality of memory cells arranged in a matrix pattern includes a plurality of reference cells, a reference voltage supply, and differential type sensing amplifiers connected to output lines of the memory cells and to an output line of the reference cells. In one embodiment the storage capability of each memory cell is tested by comparing the cell voltage to the reference voltage by selectively connecting the reference cell output line with the sensing amplifier associated with the column containing the cell under test. A memory cell is determined to be defective when the difference between the cell voltage and the reference voltage, that is, the output of the differential sensing amplifier, is below a predetermined value.

REFERENCES:
patent: 4301518 (1981-11-01), Klaas
E. C. Jacobson, IBM Tech. Discl. Bulletin, vol. 19, No. 11, Apr. 1977, pp. 4197-4198.

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