Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

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Details

365156, 365190, G11C 1140, G11C 11419

Patent

active

061282170

ABSTRACT:
A semiconductor memory device in an SRAM using a 4 transistor-type memory cell which device includes an error writing protection circuit for preventing any information from being written into a memory cell into which any information is not needed to be written owing to line capacitance between adjacent bit lines. The error writing protection circuit includes an N-type transistors, a P-type transistor, and diodes. Hereby, it is determined whether or not a bit line is charged with electricity in accordance with electric potential of an adjacent bit line, and there is not charged with electricity a bit line for which there is no possibility of any information from being written, but there is charged with electricity only bit lines where there is possibility of any information being written in error. Thus, there is flowed no excess current.

REFERENCES:
patent: 4692900 (1987-09-01), Ooami et al.
patent: 5068828 (1991-11-01), Miyaoka et al.

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