Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1995-04-19
1996-12-17
Westin, Edward P.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
326 32, 326 86, 333 22R, H03K 1716, H03K 190944
Patent
active
055857418
ABSTRACT:
A low capacitance impedance emulator suitable for active conductor termination. The impedance emulator includes an emulating FET and a control circuit coupled to the gate of the emulating FET for maintaining the FET in a linear region of operation. The control circuit includes a control FET, an impedance setting resistor, and an amplifier. The control FET is driven in a closed-loop fashion so that the impedance of the control FET has a known relationship with respect to that of the resistor. The output of the amplifier controls the conduction of both the emulating and control FETs so that the emulating FET provides an impedance proportional to that of the control FET and thus, related to the impedance of the resistor. A disconnect feature is provided, whereby the impedance emulator is responsive to a disconnect signal for disconnecting the impedance provided by the emulating FET. The impedance provided by the emulating FET is selectable by adjusting the impedance setting resistor or, in one embodiment, the impedance is selectable in response to an impedance selection signal which causes one of a plurality of FETs to operate as the emulating FET. An NMOS FET having features providing enhanced ESD performance is also provided.
REFERENCES:
patent: 3937988 (1976-02-01), DeClue et al.
patent: 4109117 (1978-08-01), Wrench, Jr.
patent: 4386242 (1983-05-01), Seidel
patent: 4553050 (1985-11-01), Feinberg et al.
patent: 4595923 (1986-06-01), McFarland, Jr.
patent: 4631721 (1986-12-01), Ono et al.
patent: 4675551 (1987-06-01), Stevenson et al.
patent: 4707620 (1987-11-01), Sullivan et al.
patent: 4719369 (1988-01-01), Asano et al.
patent: 4748426 (1988-05-01), Stewart
patent: 4831283 (1989-05-01), Newton
patent: 4857002 (1989-08-01), Jensen et al.
patent: 4859877 (1989-08-01), Cooperman et al.
patent: 4864291 (1989-09-01), Korpi
patent: 4890271 (1989-12-01), Stohs
patent: 4920339 (1990-04-01), Friend et al.
patent: 4954089 (1990-09-01), Jensen et al.
patent: 5029284 (1991-07-01), Feldbaumer et al.
patent: 5099137 (1992-03-01), Lattin, Jr.
patent: 5117331 (1992-05-01), Gebara
patent: 5124580 (1992-06-01), Matthews et al.
patent: 5136187 (1992-08-01), Ceccherelli et al.
patent: 5159297 (1992-10-01), Tateno
patent: 5164663 (1992-11-01), Alcorn
patent: 5166561 (1992-11-01), Okura
patent: 5208562 (1993-05-01), Schirm, IV
patent: 5237567 (1993-08-01), Nay et al.
patent: 5239559 (1993-08-01), Brach et al.
patent: 5239658 (1993-08-01), Yamamuro et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5283479 (1994-02-01), Rosseel et al.
patent: 5329184 (1994-07-01), Redfern
patent: 5422608 (1995-06-01), Levesque
patent: 5448081 (1995-09-01), Malhi
Sartamauro Jon
Unitrode Corporation
Westin Edward P.
LandOfFree
Impedance emulator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Impedance emulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Impedance emulator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1994187