Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1995-06-07
1997-08-26
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257642, 257637, 257760, 257759, H01L 5100
Patent
active
056613440
ABSTRACT:
A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 31 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 14 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric. A via passivating layer 30 is conformally deposited and then anisotropically etched to clear the bottom of the vias while leaving a passivating liner in the via, preventing the via metal from directly contacting the porous material. A second application of these steps may be used to form a second, overlying structure of patterned conductors 38, encapsulating layer 36, porous dielectric layer 40, and cap layer 42.
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Cho Chih-Chen
Gnade Bruce E.
Havemann Robert H.
Crane Sara W.
Donaldson Richard L.
Harris James E.
Stoltz Richard A.
Texas Instruments Incorporated
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