Semiconductor device with lightly doped drain regions

Details Semiconductor device with lightly doped drain regions Semiconductor device with lightly doped drain regions

1995-04-14

1997-02-25

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257370, 257371, 257408, H01L 27088

Patent

active

056061919

ABSTRACT:
A method and structure therefor for the formation of lightly doped drain regions, typically used in the manufacture of a field effect devices. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 20 degrees and greater from a perpendicular to the gate electrodes into both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well, and a buried region in the N type well. Sidewall spacers are then formed on edges of the gate electrodes. An N type implant step is then performed on the P type well region to form the source/drain region of a NMOS device. The method then performs two separate P type implants into the N type well, each at different angles and dosages, to form the P type LDD source/drain region for a PMOS device. The PMOS device includes the buried region which acts as a punchthrough stop, typically used to decrease short channel effects.

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