Methods and apparatus for providing a negative delay on an IC ch

Details Methods and apparatus for providing a negative delay on an IC ch Methods and apparatus for providing a negative delay on an IC ch

1994-11-30

1996-11-26

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326101, 327156, H03K 19096

Patent

active

055789455

ABSTRACT:
An integrated circuit chip on which a relatively large on-chip delay is provided using a relatively small delay in conjunction with a phase-locked-loop, whereby the relatively large variations typical of large on-chip delays are avoided.

REFERENCES:
patent: 5072195 (1991-12-01), Graham et al.
patent: 5073730 (1991-12-01), Hoffman
patent: 5295164 (1994-03-01), Yamamura
patent: 5307381 (1994-04-01), Ahuja
patent: 5420544 (1995-05-01), Ishibashi

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