Multi-stack memory architecture

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

711120, 711170, G06F 1208

Patent

active

061382108

ABSTRACT:
The present invention provides a unique multi stack memory system to provide access to multiple portions of the method frames of a stack based computing system. In one embodiment of the invention, a multi-stack memory system includes a first stack configured to store a first frame component of a first method frame and a second frame component of a second method frame. A second stack is configured to store a second frame component of the first method frame and a first frame component of second method frame. The first frame component of the method frames can be for example an operand stack. The second frame components of the method frames can be, for example, arguments and local variable areas.

REFERENCES:
patent: 3810117 (1974-05-01), Healey
patent: 3878513 (1975-04-01), Werner
patent: 3889243 (1975-06-01), Drimak
patent: 3924245 (1975-12-01), Eaton et al.
patent: 4268903 (1981-05-01), Miki et al.
patent: 4354232 (1982-10-01), Ryan
patent: 4375678 (1983-03-01), Krebs, Jr.
patent: 4524416 (1985-06-01), Stanley et al.
patent: 4530049 (1985-07-01), Zee
patent: 4600986 (1986-07-01), Sheuneman et al.
patent: 4674032 (1987-06-01), Michaelson
patent: 4761733 (1988-08-01), McCrocklin et al.
patent: 4811208 (1989-03-01), Myers et al.
patent: 4951194 (1990-08-01), Bradley et al.
patent: 5043870 (1991-08-01), Ditzel et al.
patent: 5093777 (1992-03-01), Ryan
patent: 5107457 (1992-04-01), Hayes et al.
patent: 5142635 (1992-08-01), Saini
patent: 5157777 (1992-10-01), Lai et al.
patent: 5210874 (1993-05-01), Karger
patent: 5485572 (1996-01-01), Overly
patent: 5535350 (1996-07-01), Maemura
patent: 5603006 (1997-02-01), Satake et al.
patent: 5634027 (1997-05-01), Saito
patent: 5636362 (1997-06-01), Stone et al.
patent: 5687336 (1997-11-01), Shen et al.
patent: 5784553 (1998-07-01), Kolawa et al.
Microsoft Press Computer Dictionary, 2nd Ed., p. 279, 1994.
Electronic Engineering, vol. 61, No. 750, Jun. 1989, p. 79, XP000033120, "Up Pops A 32Bit Stack Microprocessor."
Atkinson, R.R., et al., "The Dragon Processor", Second International Conference on Architectural Support for Programming Languages and Operating Systems, No. 1987, Oct 5, 1987, pp. 65-69, XP000042867.
Stanley, et al., "A Performance Analysis of Automatically Managed Top of Stack Buffers", 14th Annual International Symposium on Computer Architecture, Jun. 2, 1987, pp. 272-281, XP002032257.
Burnley, P: "CPU Architecture for Realtime VME Systems", Microprocessors and Microsystems, London, GB, vol. 12, No. 3; Apr. 1988; pp. 153-158; XP000002633.
Lopriore, L: "Line Fetch/Prefetch in a Stack Cache Memory", Microprocessors and Microsystems, vol. 17, No. 9, Nov. 1, 1993, pp. 547-555, XP00413173.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multi-stack memory architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-stack memory architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-stack memory architecture will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1975719

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.