High performance trench EEPROM cell

Details High performance trench EEPROM cell High performance trench EEPROM cell

1992-03-23

1994-05-24

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257321, 257513, H01L 2978

Patent

active

053151429

ABSTRACT:
The objects of the present invention are accomplished by merging a MOSFET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases the coupling between the floating-gate and the control-gate. A control gate overlies the floating gate and the control gate is separated from the floating gate by a separate dielectric layer. The second silicon dioxide layer is relatively thin so that tunneling of electrons between the vertical sidewalls which incorporate the source and drain regions and the floating gate will occur. Tunnelling is the mechanism which charges and discharges the floating gate. The trench EEPROM memory structure of the present invention occupies a small amount of surface area while maintaining a high coupling ratio between the control gate and the floating gate. The high coupling ratio between the floating-gate and the control-gate is maintained because the floating gate is butted to isolation oxide on two sides of the trench. The trench EEPROM memory structure of the present invention also reduces program and erase time because the floating gate can be programmed or charged through either the source or drain regions in many cells at one time.

REFERENCES:
patent: 4456978 (1984-06-01), Morley et al.
patent: 4796228 (1989-01-01), Baglee
patent: 4814840 (1989-03-01), Kameda
patent: 4929988 (1990-05-01), Yoshikawa
patent: 4964080 (1990-10-01), Tzeng
patent: 4975384 (1990-12-01), Baglee
patent: 4979004 (1990-12-01), Esquivel et al.
patent: 4990979 (1991-02-01), Otto

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