Semiconductor topography including integrated circuit gate condu

Details Semiconductor topography including integrated circuit gate condu Semiconductor topography including integrated circuit gate condu

1999-01-26

2000-10-24

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 257377, 257385, 257412, 257413, 257758, 438657, H01K 2976

Patent

active

061371459

ABSTRACT:
A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal. The first gate conductor may be doped with a first dopant that has a lower diffusion rate through polysilicon than a second dopant with which the second gate conductor is doped. The second polysilicon layer portion of the second gate conductor is substantially free of implanted dopants.

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