Self-aligned dual thickness cobalt silicide layer formation proc

Details Self-aligned dual thickness cobalt silicide layer formation proc Self-aligned dual thickness cobalt silicide layer formation proc

1998-10-22

2000-10-24

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438683, 438649, 438558, 438533, 438584, 438586, H01L 2144

Patent

active

061367052

ABSTRACT:
A process for the controlled formation of self-aligned dual thickness cobalt silicide layers during the manufacturing of a semiconductor device that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, a semiconductor device structure (such as an MOS transistor) is first provided. The semiconductor device structure includes exposed silicon substrate surfaces (such as shallow drain and source regions) and a silicon layer structure disposed above the semiconductor substrate surface (such as a polysilicon gate). A cobalt layer is then deposited over the semiconductor device structure followed by the deposition of a titanium capping layer. Next, the thickness of the titanium capping layer above the silicon layer structure (e.g. a polysilicon gate) is selectively reduced using, for example, chemical mechanical polishing techniques. Cobalt from the cobalt layer is subsequently reacted with silicon from the exposed silicon substrate surfaces to form a first self-aligned cobalt silicide layer on these surfaces. At the same time, cobalt from the cobalt layer is reacted with silicon from the silicon layer structure to form a second self-aligned cobalt silicide layer thereon, which is thicker than the first self-aligned cobalt silicide layer.

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