Process for forming metal interconnect structures for use with i

Details Process for forming metal interconnect structures for use with i Process for forming metal interconnect structures for use with i

1995-08-18

1998-05-26

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438661, 438667, 438975, H01L 21283

Patent

active

057563950

ABSTRACT:
A process for forming an integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure. The one or more layers of metal interconnects are formed on the second substrate by the steps of forming a pattern of metal contacts in the second substrate and level with the surface of the substrate; forming a metal layer over the substrate, preferably of a different metal than the metal contacts; patterning the metal layer to form vias; forming a first layer of dielectric material on the surface of the substrate over the exposed portions of the metal contacts and around the metal vias; forming a further metal layer over the first layer of dielectric material and the metal vias, preferably using a different metal than used for the metal vias; patterning the further metal layer into metal interconnects; and depositing a second layer of dielectric material over the exposed portions of the first layer of dielectric material and around the metal interconnects. In a preferred embodiment, over the uppermost metal layer is formed a layer of low melting alloy material (solder) prior to the step of patterning this metal layer to facilitate the electrical connection of the metal interconnect structure.

REFERENCES:
patent: 3811183 (1974-05-01), Celling
patent: 4489478 (1984-12-01), Sakurai
patent: 4499655 (1985-02-01), Anthony
patent: 4660066 (1987-04-01), Reid
patent: 4818728 (1989-04-01), Rai et al.
patent: 4825284 (1989-04-01), Soga et al.
patent: 5166097 (1992-11-01), Tanielian
patent: 5281151 (1994-01-01), Arima et al.
patent: 5352926 (1994-10-01), Andrews
patent: 5387817 (1995-02-01), Ishikiriyama
patent: 5475236 (1995-12-01), Yoshizaki
patent: 5475264 (1995-12-01), Sudo et al.
patent: 5485039 (1996-01-01), Fujita et al.
patent: 5508561 (1996-04-01), Tago et al.
patent: 5510655 (1996-04-01), Tanielian
patent: 5510758 (1996-04-01), Fujita et al.
patent: 5615477 (1997-04-01), Sweitzer
Wolf, S., Silicon Processing, vol. 2, 1990, Lattice Press, pp. 176-189, 240-251, 258-259, 1990.

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