Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1996-03-11
1999-02-09
Saadat, Mahshid D.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257751, 257752, 257758, 257763, 257764, 257765, 257767, 257770, 257774, 257775, H01L 2348, H01L 2352, H01L 2940
Patent
active
058699023
ABSTRACT:
A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via), a reactive spacer formed on the sidewall of the opening or a reactive layer formed on the sidewall and on the bottom surface of the opening and a first conductive layer formed on the insulating layer which completely fills the opening. Since the reactive spacer or layer is formed on the sidewall of the opening, when the first conductive layer material is deposited, large islands will form to become large grains of the sputtered Al film. Also, providing the reactive spacer or layer improves the reflow of the first conductive layer during a heat-treating step for filling the opening at a high temperature below a melting temperature. Thus, complete filling of the opening with sputtered Al can be ensured. All the contact holes, being less than 1 .mu.m in size and having an aspect ratio greater than 1.0, can be completely filled with Al, to thereby enhance the reliability of the wiring of a semiconductor device.
REFERENCES:
patent: 4589196 (1986-05-01), Anderson
patent: 4630357 (1986-12-01), Rogers et al.
patent: 4641420 (1987-02-01), Lee
patent: 4720908 (1988-01-01), Wills
patent: 4963511 (1990-10-01), Smith
patent: 4970176 (1990-11-01), Tracy et al.
patent: 4983547 (1991-01-01), Arima et al.
patent: 5071791 (1991-12-01), Inoue et al.
patent: 5213989 (1993-05-01), Fitch et al.
patent: 5266521 (1993-11-01), Lee et al.
patent: 5317187 (1994-05-01), Hindman et al.
patent: 5534463 (1996-07-01), Lee et al.
patent: 5589713 (1996-12-01), Lee et al.
W.Y-C Lai, et al., "CVD Aluminum for Submicro-VLSI Metallization" 1991 Proc. 8th International Conference (Jun. 11-12, 1991) pp. 89-95.
Hisako Ono et al., "Development of a Planarzdie Al-Si Contact Filling Technology", VMIC Conference, Jun. 12, 1990, pp. 76-82.
Dipankar Pramanik et al., "Effect of Underlayer on Sputtered Aluminum Grain Structure and Its Correlation with Step Coverage in Submicron Vias", VMIC Conference, Jun. 12, 1990, pp. 332-334.
C.S. Park et al., "A1-Plaph (Aluminum-Planarization by Post-Heating) Process for Planarized Double Metal CMOS Applications", VMIC Conference, Jun. 12, 1991, pp. 326-328.
H.P. Kattelus et al., "Bias-induced Stress Transitions in Sputtered TiN Films", J. Vac Sci. Technol. vol. 4, Jul./Aug. 1986, pp. 1850-1854.
Lee Sang-in
Park Chang-soo
Clark Jhihan B.
Saadat Mahshid D.
Samsung Electronics Co,. Ltd.
LandOfFree
Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1951844