FET semiconductor integrated circuit device having a planar elem

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257773, 257776, H01L 2712

Patent

active

058698671

ABSTRACT:
In a semiconductor device, an extra wiring area generated by the connection of an upper layer wiring to an element on a semiconductor substrate is reduced to improve the level of integration, and the parasitic capacitances between the gate and the source-drain regions are reduced to enhance the performance of the circuit.
A gate electrode is formed via a gate insulating film on a semiconductor layer formed in the semiconductor substrate. This semiconductor layer is for forming the source region and the drain region, where the source region and the drain region are formed on the left and right of the gate electrode with the gate electrode at the center. Wirings connected to the source region are formed on the same side of the gate electrode. Wirings connected to the drain region are formed on the opposite side of the gate electrode with the semiconductor layer in between.

REFERENCES:
patent: 4902637 (1990-02-01), Kondou et al.
patent: 5041884 (1991-08-01), Kumamoto et al.
patent: 5347154 (1994-09-01), Takahashi et al.
patent: 5670812 (1997-09-01), Adler et al.
patent: 5675185 (1997-10-01), Chen et al.

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