DRAM capacitor having lower electrode and dielectric layer of sa

Details DRAM capacitor having lower electrode and dielectric layer of sa DRAM capacitor having lower electrode and dielectric layer of sa

1996-06-19

1999-02-09

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257306, 257532, H01L 27108

Patent

active

058698590

ABSTRACT:
In a DRAM memory cell built in a semiconductor device, a capacitor is formed on a field oxide film so as not to superpose upon a transistor. An area of the field oxide film can therefore be used efficiently. Since the capacitor can be formed before the transistor is formed, high temperature treatment in forming the capacitor does not give adverse effects on the transistor characteristics. The capacitor dielectric film can be made of material of a high dielectric constant. The capacitor dielectric layer and lower electrode are formed by patterning in succession with the same etching mask. The gate electrode is formed at the same time when the upper capacitor electrode is formed. At the same time when the gate oxide film is formed, an oxide film is formed also on the surface of the capacitor dielectric layer. Pin holes in the dielectric layer are buried by this oxidation. With a reduced number of processes, the additional number of manufacture processes for built-in memory cell in addition to the manufacture processes of logic circuit can be made small. A semiconductor device and its manufacture method are provided which have less load on processes and a small memory cell size.

REFERENCES:
patent: 4255756 (1981-03-01), Shimotori et al.
patent: 5111355 (1992-05-01), Anand et al.
patent: 5162890 (1992-11-01), Butler
patent: 5396095 (1995-03-01), Wolters et al.
patent: 5397729 (1995-03-01), Kayanuma et al.
patent: 5420449 (1995-05-01), Oji
patent: 5470775 (1995-11-01), Nariani
patent: 5475248 (1995-12-01), Takenaka
patent: 5498890 (1996-03-01), Kim et al.
patent: 5578848 (1996-11-01), Kwong et al.
"Adding Mixed-Signal Capability To A Submicron Digital Asic Process", Subhash R. Nariani, et al., Solid Technology, Aug. 1994, pp. 79-83.

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