Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-03-13
1999-02-09
Chaudhuri, Olik
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257288, 257316, 257622, H01L 27108, H01L 2976, H01L 2994, H01L 31119
Patent
active
058698582
ABSTRACT:
A semiconductor device comprises a substrate, a first conductive layer formed on the substrate and comprising a first layer and a second layer formed on the first layer and having at least one of a convex and a concave, an insulating layer formed on the one of the convex and the concave of the first conductive layer, and a second conductive layer formed opposed to the one of the convex and the concave with the insulating layer interposed therebetween to thereby form a capacitive element with the first conductive layer, the insulating layer having a first region having a first capacitance value per unit area that substantially determines the capacitance value of the capacitive element and a second region having a second capacitance value per unit area that is smaller than the first capacitance value per unit area of the first region, and the second region being formed on the first layer of the conductive layer which is exposed to the one of the convex and the concave.
REFERENCES:
patent: 4262296 (1981-04-01), Shealy et al.
patent: 4897702 (1990-01-01), Sunouchi
patent: 5307310 (1994-04-01), Narita
patent: 5471423 (1995-11-01), Iwasa
patent: 5563105 (1996-10-01), Dobuzinsky et al.
patent: 5563762 (1996-10-01), Leung et al.
Folberth, O. G. "Transistor with Tunnel Gate", IBM Tech. Disc. Bull., vol. 16, No. 12, p. 3953, May 1974.
Kunio Nakamura, et al., "Buried Isolation Capacitor (BIC) Cell for Megabit MOS Dynamic RAM", IEEE IEDM Tech Digest, (pp. 236-239), Dec. 1984.
K. Sekiya, et al., "Trench Self-Aligned Eprom Technology", Symposium on VLSI Technology Technical Digest, (pp. 87-88), 1986.
W.F. Richardson, et al., "A Trench Transistor Cross-Point Dram Cell", IEEE IEDM Tech Digest, (pp. 714-717), Dec. 1985.
M. Sakamoto, et al., "Buried Storage Electrode (BSE) Cell for Megabit Drams", IEEE IEDM Tech Digest, (pp. 710-713), Dec. 1985.
N. Lu, et al., "The SPT Cell--A New Substrate-Plate Trench Cell for Drams", IEEE IEDM Tech Digest, (pp. 771-772), Dec. 1985.
Yosiaki S. Hisamune, et al., "A 3.6 .mu.m.sup.2 Memory Cell Structure for 16MB EPROMS", IEEE IEDM Tech Digest, (pp. 583-586), 1989.
Ozawa Yoshio
Saida Shigehiko
Chaudhuri Olik
Kabushiki Kaisha Toshiba
Weiss Howard
LandOfFree
Semiconductor device for reducing variations in characteristics does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device for reducing variations in characteristics , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device for reducing variations in characteristics will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1951386