Method of manufacturing a semiconductor device with a stacked vi

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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257758, H01L 214763

Patent

active

061272655

ABSTRACT:
After forming the first contact embedded in the first insulating film, a wire is formed on the first contact and a side wall made of an insulative substance is formed on a side surface of the wire. The second insulating film made of a substance different from the side wall is layered in a region including the wire, and a via hole for embedding the second contact is provided in the second insulating film under such an etching condition that the side wall is harder to etch, and therefore an end portion of the wire is not etched and an exposed area of an internal wall of the via hole can be reduced. It is possible to suppress deterioration gap-filling characteristics due to gas discharge from the second insulating film and achieve a contact of good shape. Thus, this structure avoids deterioration in imbedding characteristics that is caused by a deviation of alignment when the wire is interposed between a stacked via consisting of the first and second contacts.

REFERENCES:
patent: 5399527 (1995-03-01), Tabara
patent: 5451543 (1995-09-01), Woo et al.
patent: 5629236 (1997-05-01), Wada et al.
patent: 5864179 (1999-01-01), Koyama
patent: 5874779 (1999-02-01), Matsuno
patent: 6023083 (2000-02-01), Tomita
patent: 6023101 (2000-02-01), Tomita

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