Semiconductor device and manufacturing method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257402, 257408, H01L 2910, H01L 2978

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active

052182215

ABSTRACT:
A semiconductor device which includes a MOS type transistor has impurity ion implanted regions (4) of the same conductivity type as that of the semiconductor substrate (1) for controlling a threshold voltage of a channel region, at least in the vicinity of a channel region provided between the source/drain regions (6, 8) on the surface of the semiconductor substrate (1). In the device the concentration distribution in the impurity ion-implanted regions (4) is higher in the vicinity of opposite ends of the channel region and lower in a central portion of the channel region. By employing the structure of this semiconductor device, while holding a suitable threshold voltage, a high potential barrier is formed at both ends of the channel region, so that insulating breakdown voltage of the source/drain regions (6, 8) is increased. A semiconductor device of said structure is manufactured by implanting impurity ions at a predetermined tilt angle with a semiconductor substrate (1) rotating, using the transfer gate electrode (5) as a mask.

REFERENCES:
Kawabuchi, et al., IEEE Transactions on Electron Devices, vol. ED-32, No. 9, Sep. 1985, pp. 1685-1687.
Fuse, et al., J. Electrochem. Soc.: Solid-State Science and Technology, pp. 996-998.
Hori, et al., IEEE Electron Device Letters, vol. 9, No. 12, Dec. 1988, pp. 641-643.
Odanaka, et al., IEEE Transactions on Electron Devices, vol. ED-33, No. 3, Mar. 1986, pp. 317-321.
Hori, IEDM 89-777, pp. 777-780, Dec. 1989.
Hori, et al., IEEE Electron Device Letters, vol. 9, No. 6, Jun. 1988, pp. 300-302.
Fuse, et al., IEEE Transactions on Electron Devices, vol. ED-34, No. 2, Feb. 1987, pp. 356-359.
(K.K.) Kogyochosa-Kai, Electronics-Zenshu (8) Ion Implantation Technique.
Shibata et al., "High Performance Half-Micron PMOSFETs With 0.1 .mu.m Shallow P+N Junction Utilizing Selective Silicon Growth and Rapid Thermal Annealing", IEDM 1987, pp. 590-593.

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