Controlling dynamic memory refresh cycle time

Details Controlling dynamic memory refresh cycle time Controlling dynamic memory refresh cycle time

1993-07-13

1995-02-21

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365194, G11C 1140

Patent

active

053922514

ABSTRACT:
Self refresh timing in a low-power dynamic memory system is governed by an oscillator having a voltage dependent resistor and a process dependent capacitor. The resistor increases in resistance to compensate for increased applied power supply voltage and variation in substrate bias voltage. The total capacitance needed for a given oscillator center frequency is made up of a plurality of capacitors having the same physical characteristics as the capacitor used in the dynamic memory cell. Power supply voltage, substrate bias voltage, and the physical characteristics of the cell capacitor affect the cell's data retention time. By compensating the oscillator for these effects, refreshing is optimally accomplished within the data retention time. A system having compensated refresh timing according to the invention is more appropriate for low power applications due to the resulting decreased power consumption.

REFERENCES:
patent: 4406013 (1983-10-01), Reese et al.
patent: 4716551 (1987-12-01), Inagaki
patent: 4901283 (1990-02-01), Hanbury et al.
patent: 4982369 (1991-01-01), Tatematsu
patent: 5033026 (1991-06-01), Tsujimoto
patent: 5278797 (1994-01-01), Jean et al.

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