Method for forming local interconnect for integrated circuits

Details Method for forming local interconnect for integrated circuits Method for forming local interconnect for integrated circuits

1993-10-18

1995-02-21

Quach, T. N.

Fishing, trapping, and vermin destroying

437190, 437192, 437 59, 148DIG19, H01L 21283, H01L 21302

Patent

active

053915208

ABSTRACT:
A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer is formed over the integrated circuit. A barrier layer is formed over the refractory metal layer, and optionally a refractory metal silicide layer is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed. The refractory metal layer and barrier layer, and the refractory metal silicide layer if formed, are etched to define a conductive interconnect between the exposed selected regions of the first and second conductive structures.

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