Cache controller fault tolerant computer and data transfer syste

Details Cache controller fault tolerant computer and data transfer syste Cache controller fault tolerant computer and data transfer syste

1997-10-10

2000-05-30

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

714 5, 714763, 714 34, G06F 1100

Patent

active

06070232&

ABSTRACT:
A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

REFERENCES:
patent: 4905196 (1990-02-01), Kirrmann
patent: 5257370 (1993-10-01), Letwin

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