Element isolation structure of a semiconductor device to suppres

Details Element isolation structure of a semiconductor device to suppres Element isolation structure of a semiconductor device to suppres

1996-11-12

2000-02-15

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257349, 257354, H01L 2900

Patent

active

06025629&

ABSTRACT:
A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

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patent: 5652453 (1997-07-01), Iwamatsu et al.
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