Semiconductor memory device having circuit for prevention of ove

Details Semiconductor memory device having circuit for prevention of ove Semiconductor memory device having circuit for prevention of ove

1990-06-22

1992-12-29

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

365203, 36518909, G11C 1140, G11C 1606

Patent

active

051757052

ABSTRACT:
A semiconductor memory device comprises row lines, memory cells selectively driven by the row lines, and a column line connected to the memory cells. A load transistor is connected to the column line. A source/drain current path of a first transistor is connected between the column line and the load transistor. The gate potential of the first transistor is controlled by an output of an inverter. An input of the inverter is connected to the column line. A discharge circuit is also connected to the column line. When the potential on the column line is above a predetermined potential, the column line is discharged by the discharge circuit until the potential on the column line becomes equal to the predetermiend potential.
For the predetermined potential, a potential obtained by subtracting the threshold voltage of the first transistor from the gate voltage thereof, may be used. By employing the construction described above, there is provided a semiconductor memory device having a mechanism for the prevention of an overcharge operation of the column line.

REFERENCES:
patent: 4417328 (1983-11-01), Ochii
patent: 4542485 (1985-09-01), Iwahashi et al.
patent: 4694429 (1987-09-01), Tanaka et al.
patent: 4769784 (1988-09-01), Doluca et al.
patent: 4797856 (1989-01-01), Lee et al.

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