Bit line selection circuit

Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge

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Details

365203, 365227, G11C 700

Patent

active

057814872

ABSTRACT:
An improved bit line selection circuit which is capable of preventing power consumption of Vpp by delaying an external signal for a predetermined time, first turning off the NMOS transistor connected to Vcc, turning on the PMOS transistor connected to Vpp, and preventing a formation of a current path from Vpp to Vcc, which incudes a control signal generation unit for generating a control signal by operating an external signal inputted thereto through an input node, the control signal generation unit being symmetrical; first and second bit line selection signal generation unit for generating a bit line selection signal of Vpp level in accordance with a control of the control signal generation unit; and an electric charge charging unit for charging a part of electric charges when a selection signal of the first or second bit line selection signal is discharged from Vpp to Vcc, recycling electric charge which is charged when selecting a bit line, and precharging a bit line selection signal.

REFERENCES:
patent: 5359555 (1994-10-01), Salter, III
patent: 5418748 (1995-05-01), Monden
patent: 5539700 (1996-07-01), Kawahara
patent: 5631822 (1997-05-01), Naritake et al.

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