Semiconductor memory device with a two-layer top gate

Details Semiconductor memory device with a two-layer top gate Semiconductor memory device with a two-layer top gate

1997-08-04

1998-07-14

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257388, 257903, 257904, H01L 29786

Patent

active

057809097

ABSTRACT:
The present invention provides a semiconductor memory device including (a) a substrate, (b) a first MOS transistor acting as a driver, the first MOS transistor being formed on the substrate, (c) a second MOS transistor acting as a load, the second MOS transistor being formed on an insulative layer formed on the substrate, and (d) a gate electrode formed on a gate insulating film above a channel region of the second MOS transistor, the gate electrode comprising a semiconductor layer and a layer composed of metallic compound thereof. The present invention avoids significant reduction of breakdown voltage of a gate electrode in SRAM including a p-channel TFT as a load, even if a gate insulating film of a p-channel TFT is made thin.

REFERENCES:
patent: 5266587 (1993-11-01), Wu
patent: 5281843 (1994-01-01), Ochii et al.
patent: 5382807 (1995-01-01), Tsutsumi et al.
patent: 5391894 (1995-02-01), Itabashi et al.
patent: 5483083 (1996-01-01), Meguro et al.
patent: 5491654 (1996-02-01), Azuma
patent: 5497022 (1996-03-01), Sakamoto
patent: 5535155 (1996-07-01), Abe
"16Mbit SRAM Cell Technologies for 2.0V Operation," H. Ohkubo et al., IEDM Technical Digest, 1991, pp. 481-484.
"Improvement of Soft Error Immunity in a Polysilicon PMOS Load Memory Cell," Kiyotsugu Ueda et al., Article C-427, Electronic Communication Association Autumn Meeting, 1991.

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