Semiconductor device having triple wells

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257345, H01L 2976, H01L 2994

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active

057809070

ABSTRACT:
A semiconductor device including a semiconductor substrate 10 of a first conduction-type, first wells 20a, 20b of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate 10, a second well 22a formed in a second region on the primary surface of the semiconductor substrate 10 other than the first region, a third well 22b of the first conduction-type formed in the first well, and high-concentration impurity-doped layers 26 of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In a semiconductor device having triple wells, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration. As a result, punch-through between the source/drain diffused layer of the transistor formed in an inner well of a double well, and the well outside of the double well can be prevented. This structure is also effective to prevent latch-up.

REFERENCES:
patent: 5373476 (1994-12-01), Jeon
patent: 5514889 (1996-05-01), Cho et al.
Genus, Inc. Presents: "The 1990's Smart and Economic Device and Process Desings for ULSI Technology", Parc Fifty-Five Hotel, San Francisco, CA, Jul. 21, 1993.
H. Mikoshiba, "A novel CMOS Process Utilizing After-Gate-Implantation Process", 1986 Symposium on VLSI technology.
John Ogawa et al., "MeV implantation technology: Next generation manufacturing with current-generation equipment", Solid State Technology, pp. 28-35.

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