Semiconductor device having shallow impurity region without shor

Details Semiconductor device having shallow impurity region without shor Semiconductor device having shallow impurity region without shor

1996-12-19

1998-07-14

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, 257408, 257410, 257900, H01L 2978, H01L 2960

Patent

active

057808961

ABSTRACT:
Elevated source and drain regions epitaxially grown on both sides of a gate structure cause a dopant impurity to form an extremely shallow p-n junctions in a semiconductor substrate so as to prevent a field effect transistor from a short channel effect, and side wall spacers include pad layers of silicon nitride and spacer layers of silicon oxide formed on the pad layers so that the elevated source and drain regions form boundaries to the pad layers without a facet and a silicon layer on the spacer layers.

REFERENCES:
patent: 4818714 (1989-04-01), Haskell
patent: 4951100 (1990-08-01), Parrillo
patent: 5182619 (1993-01-01), Pfiester
patent: 5324974 (1994-06-01), Liao
patent: 5521411 (1996-05-01), Chen et al.
patent: 5670804 (1997-09-01), Usagawa et al.
Kimura et al., "A 0.1 Micorm-gate Elevated Source and Drain MOSFET Fabricated By Phase-shifted Lithography", Technical Digest of IEDM, pp. 950-952, (1991) no month.

Affiliated with

Also associated with

Rating

Semiconductor device having shallow impurity region without shor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having shallow impurity region without shor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having shallow impurity region without shor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1884734