Programmable logic array system incorporating Josephson devices

Details Programmable logic array system incorporating Josephson devices Programmable logic array system incorporating Josephson devices

1980-06-30

1982-11-23

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Superconductive

365160, G11C 1144

Patent

active

043608981

ABSTRACT:
A Programmable Logic Array (PLA) system which utilizes Josephson devices and the noninverting capabilities of these devices is disclosed. The disclosed PLA system includes a personalized Read Only Memory (ROM) which is adapted to store the applied input signals as well as the output signals which are a logic function of the input signals. As soon as outputs from the ROM are available, an interface circuit which may be timed or untimed, inverting or noninverting provides output signals which can be utilized to drive other logic circuits or to act as inputs to another personalized Read Only Memory (ROM). The latter provides another logic function of the inputs at its outputs. Again, the outputs may be used directly or applied to another interface circuit which itself may provide inverted or noninverted outputs.
Like the first mentioned ROM, the second mentioned ROM is capable of storing its inputs and the resulting outputs which are some logic function of the inputs as a result of the ROM personalization. The ROM's involved utilize memory cells which are programmable Josephson junction devices operating in a liquid helium environment.
The programmable logic array system is disclosed in a full adder embodiment which is dc powered. A similar hybrid embodiment using both ac and dc power is also shown. The resulting system using high density ROM's provides high speed logic using relatively standard loop circuits which minimize the effect of the presence of resonances of known random logic circuits.

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IBM Tech. Dis. Bul., vol. 17, No. 7, Dec. 1974, "Personalization Approach for Josephson Array Logic Memory Cells", Terlep, pp. 2059-2060.
IBM Tech. Dis. Bul., vol 20, No. 10, Mar. 1978, "Coupling Element for Josephson Read-Only Memory", Faris, pp. 4197-4198.
"Model for a 15 NS 16K RAM with Josephson Junctions", R. F. Broom, IEEE Journal of Solid State Circuits, vol. SC-14, No. 4, Aug. 1979, pp. 690-699.
"Basic Design of Josephson Technology Cache Memory", S. M. Faris et al., IBM Journal of R & D, vol. 24, No. 2, Mar. 1980, pp. 143-154.

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