Method and apparatus for providing a high speed tristate buffer

Details Method and apparatus for providing a high speed tristate buffer Method and apparatus for providing a high speed tristate buffer

1996-12-30

1999-05-04

Tokar, Michael J.

Electronic digital logic circuitry

Tri-state

With field-effect transistor

326 57, 326 97, H03K 1902, H03K 19096

Patent

active

059007443

ABSTRACT:
A method and apparatus for providing a high speed tristate buffer. The buffer includes a p-channel pull-up transistor and a transfer gate. The source of the transistor is coupled to a voltage supply. The drain of the transistor is coupled to the buffer output. The gate of the transfer gate is coupled to a first clock source. The input to the transfer gate is a second clock source, and the output of the transfer gate is coupled to the gate of the p-channel transistor.

REFERENCES:
patent: 5491432 (1996-02-01), Wong et al.
patent: 5510732 (1996-04-01), Sandhu
patent: 5682110 (1997-10-01), Rountree

Affiliated with

Also associated with

Rating

Method and apparatus for providing a high speed tristate buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for providing a high speed tristate buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for providing a high speed tristate buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1871754