Semiconductor device with self-aligned protection diode

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257355, 257360, 257362, H01L 2362

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active

059006641

ABSTRACT:
A self-aligned protection diode is formed at the first polycrystalline silicon level, thereby enabling in-process charging damage protection while reducing the layout area. The self-aligned protection diode is formed by providing an etch stop layer having an arcuate portion with different etching characteristics than horizontal portions, isotropically etching the arcuate portion to form a through hole exposing a side surface of a polycrystalline silicon layer and the underlying semiconductor substrate, ion implanting impurities to form the protection diode, and filling the through hole with a metal interconnecting the side surface of the polycrystalline silicon layer with the vertically self-aligned protection diode.

REFERENCES:
patent: 5587598 (1996-12-01), Hatanaka
patent: 5602410 (1997-02-01), Schwalke et al.
patent: 5672895 (1997-09-01), Iida et al.
patent: 5808365 (1998-09-01), Mori
Zheng et al., "A Quick Experimental Technique In Estimating The Cumulative Plasma Charging Current with MOSFET and Determining The Reliability of The Protection Diode In The Plasma Ambient," 1996 1st International Symposium on Plasma Process-Induced Damage (IEEE Cat. No. 96TH8142), May 1996, pp. 27-29.
H.C. Shin et al., "Thin gate oxide damage due to plasma processing," Semiconductor Science and Technology, Apr. 1996, vol. 11, No. 4, pp. 463-473.
H. Shin et al., "Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide," International Electron Devices Meeting 1993, IEEE Cat. No. 93CH3361-03, 1993, pp. 467-470.
M.C. Chang et al., "Degradation of MOS Transistor Characteristics by Gate Charging Damage During Plasma Processing," International Symposium on VLSI Technology, Systems, and Appliations, IEEE Cat. NO. 93TH0524-9, 1993, pp. 320-324.

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